Multiple layered circuits of joined adjacent circuit layers are used to make complex electrical Circuits in electronics packages. Common names for these packages include printed circuit boards (PCBs), both single and double sided, multi-chip modules, single and multiple chip carriers, ball grid arrays, chip on board assemblies, etc. These circuit layers typically include a pattern of conductive traces which are used to interconnect electrical components. The conductive traces are commonly of a conductive metal, e.g., copper, bonded to, or otherwise incorporated into, an insulating substrate, which mechanically supports the conductive traces. Insulating, substrates typically include dielectric materials that can be rigid or flexible and fabricated of materials including, for example polymers, ceramics, glasses, silicon etc. The conductive traces may be formed using any number of techniques, for example electroplating, etching, sputtering, mechanical attachment using adhesives and others. Electrical connections between components of the electrical circuits are provided on the circuit layers of the multi-layer circuit. Using, multiple circuit layers allows the circuit designer to lay out complex circuit designs using single or multiple components, that require numerous interconnections. Multiple circuit layers increase component density and functionality per unit volume.
The conductive traces in each circuit layer of a multi-layer circuit act as wires and are Used to interconnect the various components of the circuit. Electrical connection between adjacent circuit layers is achieved using, "vias". A via is created by forming a hole between adjacent circuit layers. Conductive material is then deposited on the side walls of the hole to form an electrical connection between the two adjacent circuit layers.
Typically, in printed circuit board (PCB) fabrication, otherwise known as printed wiring board or plated through hole (PTH) technology, the conductive (electrical) traces are formed separately on each layer of the multi-layer circuit board. The circuit board layers of the multi-layer circuit board are then stacked and aligned to each other with an electrically insulating bonding layer between the adjacent layers. The assembled layers are then subjected to heat and pressure to provide a bond between the adjacent layers. Via holes are then drilled in the appropriate locations where interconnect pads are desired on successive layers. The electrical interconnect is achieved by applying a conductive material to the side walls of the via holes. The prior art requires the metal via contact pads to have sufficient area on the circuit board to accommodate the drill cross section and/or any misalignment. These large pad areas limit the component density of the circuit board.
These vias are "stacked" when they extend through all of the circuit board layers from top to bottom. However, since these vias are drilled through the entire board, the vias and their target pads consume significant portions of the circuit area, limiting routing in boards with many layers. Long via columns are a reliability concern due to thermal expansion mismatch between the dielectric and the via metal. Furthermore, it is desirable to have vias much smaller in diameter than what is economically feasible to drill. To form blind and buried vias, i.e., those which pass into the top layer only or connect only adjacent layers not passing through the entire board thickness, the two or more layers are laminated first to form a sub-assembly and then drilled and plated forming connections through the dielectric. Several of these sub-assemblies are then laminated together again and a second drilling and plating operation is carried out to provide connections between the sub assemblies. To fabricate more complex multi-layered board assemblies, several of these multi-layered assemblies may be laminated, drilled and plated in a third cycle. The addition of these multiple lamination, drilling and plating steps adds significant processing costs as well as yield loss due to damage to internal vias during subsequent lamination steps and the failure of long through hole vias due to thermal expansion.
The advent of semiconductor processing and advanced materials has permitted the fabrication of circuit boards on a much finer scale than the printed circuit boards described above. Examples of these include ceramic hybrids and thin film deposited substrates, such as multi-chip modules (MCMs).
Typically, these circuits are manufactured in small numbers for aerospace, military and supercomputer applications. An example would be MCM-Ds. The D refers to deposition where a circuit is built up upon an inorganic non-conducting substrate using, thin film approaches with copper or aluminum traces and organic or inorganic dielectric. Using these technologies, a multi layer circuit is built up by a sequential process. This technology is capable of fabricating very fine lines and vias (blind, stacked, and buried) resulting, in increased circuit densities, when compared to the conventional plated through hole technology described above.
However, this increased density is at the cost of much more expensive processing, that is usually accomplished in sequential batch processing that typically includes using complex, expensive equipment. Batch processing does not lend itself to high volume production and the sequential fabrication results in lower yield as the deposition of one defective layer ruins an entire part.
To overcome some of the disadvantages of the above approaches, a number of alternative approaches to circuit interconnect (circuit assembly) construction have been developed.
Canadian Patent No. 1,307,594 and U.S. Pat. No. 5,502,884 disclose a multi-layer electronic circuit formed of electronic circuit layers metallized on both sides. The metal is then patterned with the desired circuit structures required for each layer using conventional techniques. The two electronic circuit layers are connected together by interposing an adhesive connecting layer of an insulating resin containing electrically conductive particles.
U.S. Pat. No. 5,282,312 (DiStefano et al.) discloses a two metal seeded flexible circuit patterned with plated through holes (vias). The connection between the circuit layers is made by a bond-ply with patterned conductive adhesive buttons. The buttons on the bond ply are placed on the same grid spacing as the PTHs on the flexible circuit and the bond-ply contains an impenetrable dielectric core that prevents shorting through the bond-ply. During lamination (also known as lay-up), the circuit and interposer bond-ply layers are registered to one another and the entire system is joined together. However, a drawback to this system is that the patterned interposed bond-ply layer adds cost to the system, due to the fabrication. Moreover, the exacting registration of the interposed layer to the circuit layers decreases the resultant Circuit density and yield.
U.S. Pat. No. 3,832,769 (Olaphant, Jr. et al.) discloses a method of forming a connection between adjacent layers of a printed circuit. Metal conductive columns extend from vias above the plane of the dielectric film, that contains the vias. Conductive land areas or contact pads are then bonded to the extending portions of the conductive columns. However, the joints made by the contact between the metal conductive columns and the contact pads are not sufficient to mechanically hold the circuit layers together. This is especially a problem when the dielectric material is thin and flexible and the vias of the connecting circuit layers are small in size (height and diameter) and few in number. In addition, the via connections are left exposed to the environment where they can corrode easily.
U.S. Pat. No. 5,401,913 (Gerber et al.) discloses using columns (bumps) of a rigid metal for interconnecting multiple circuit board layers in a multilayer circuit. The circuit board layers are formed by depositing a trace metal layer onto one side of a dielectric layer and making a via on the other side. The via holes are formed in the dielectric film, where a connection to an adjacent circuit board layer is desired. These via holes are then filled with a rigid non-reflowable conductive metal, as bumps that protrude from the surface of the dielectric layer. The rigid conductive bumps are then coated with an electrically conducting metal which is capable of forming a metal to metal bond between the bump and the adjacent pad to which it is expected to connect and bond thereto.
There is further disclosed deposition of an electrically insulating adhesive bonding material over the Surfaces of the circuit board layers. A plurality of these layers are then stacked, aligned and laminated together under heat and pressure in a single lamination step. The metal surfaces of the bumps and pads are bonded together, resulting in both electrical and mechanical connections.
However, the use of a rigid non reflowable conductive metal for the bumps makes rework of the bumps difficult. In addition, the rigid nature of the bumps limits the tolerable height variation of the bumps since taller bumps form pedestals preventing adjacent shorter bumps from forming good contacts. This limits the utility of the invention especially when blind and buried vias are desired.
U.S. Pat. No. 5,046,238 (Daigle et al.) discloses a fusible dielectric material that is provided with circuitry on one side and vias exposing the circuitry on the other side. A fusible conductive material is deposited in the vias. Stacking a plurality of these structures together in registration to one another, they may be laminated together under heat and pressure, fusing the conductive via material with other conductive via material and/or corresponding circuit pads and fusing the dielectric material to the rest of the circuit. A drawback to this method is that very few fusible dielectric materials are dimensionally stable enough to make a high density circuit board in this manner. Additionally, these materials are extremely expensive. As a result, forming a circuit on these fusible dielectrics requires the conductive material to be fused at high temperatures. In addition, the dielectric material must necessarily fuse at a temperature well above temperatures the substrate will see in subsequent assembly operations in order to maintain dimensional stability and remain bonded. The high fusion temperatures are commonly above the melting temperatures of more conventional low cost fusible conductors that might be used in the via, causing the via metallurgy to melt during lamination. Molten metal in the laminate is difficult to control when it melts simultaneously with the softening of a fusible dielectric, as it may be pushed out of the via area, resulting in unwanted connections between conductors that should remain isolated. Simultaneously, the conductive metal is depleted from the via where the connection is desired, thus the connection may be formed improperly, or not at all. Finally, fusion at high temperatures tends to contaminate some metallurgies on surface conductors causing problems in later assembly processes.